1. Technical Field
The embodiment described herein relates generally to a semiconductor integrated circuit (IC), and more particularly, to a delay locked loop (DLL) circuit that is included in a semiconductor IC and a method of controlling the DLL circuit.
2. Related Art
Conventional semiconductor ICs, such as synchronous dynamic random access memories (SDRAMs), are operated using a clock signal while improving an operational speed. The semiconductor IC includes a clock buffer to buffer an externally inputted clock signal and uses the buffered clock signal outputted from the clock buffer. In some cases, the semiconductor IC generates and uses an internal clock signal. In this case, a phase difference between the internal clock signal an external clock signal is corrected using a delay locked loop (DLL) circuit or a phase locked loop (PLL) circuit. For an internal clock signal that is used in the semiconductor IC, a ratio between a high interval and a low interval, i.e., a duty ratio, is preferably maintained at 50:50. However, the duty ratio of the internal clock signal may become distorted since the semiconductor IC includes a plurality of delay elements.
A clock signal having a stable duty ratio is required since availability of a clock signal increases as the operational speed of the semiconductor IC increases. Accordingly, a DLL circuit of each semiconductor IC includes a duty cycle correction apparatus to stabilize the duty ratio of a clock signal. Duty cycle correction technology has become increasingly important in order to stably use a clock signal during high-speed operation.
The conventional duty cycle correction apparatus included in a DLL circuit is disposed near a clock output terminal of the DLL circuit and detects a duty ratio of an output clock signal and corrects the duty ratio. When a clock signal having a distorted waveform due to noise is input to the DLL circuit, the clock signal can be removed while passing though a delay line of the DLL circuit, which may have a negative result. However, conventional duty cycle correction technology cannot be utilized where the input clock signal is distorted. Accordingly, the conventional duty cycle correction operation of the DLL circuit has technical limitations. As a result, it is difficult to stably support the operation of the semiconductor IC.